Compact memory structure including tunneling diode

ABSTRACT

A resonant inter-band tunnel diode (RITD) can be fabricated using semiconductor processing similar to that used for Complementary Metal-Oxide-Semiconductor (CMOS) device fabrication, such as can include using silicon. A memory cell (e.g., a random access memory (RAM) cell) can be fabricated to include one or more negative differential resistance device, such as tunneling diodes, such as to provide a single-bit or multi-bit cell. In an example, a “hybrid” memory cell can be fabricated, such as including one or more negative resistance devices, a MOS transistor structure, and a capacitor structure, such as including an integrated capacitor configuration similar to a generally-available dynamic RAM (DRAM) structure, but such as without requiring a refresh and offering a higher area efficiency.

CLAIM OF PRIORITY

This application is a divisional of U.S. application Ser. No.14/656,131, filed Mar. 12, 2015, which application claims the benefit ofpriority of each of (1) Berger, U.S. Provisional Patent Application Ser.No. 61/951,959, titled “MEMORY STRUCTURE INCLUDING RESONANT INTERBANDTUNNELING DIODE (RITD),” filed on Mar. 12, 2014 (Attorney Docket No.4089.001PRV); (2) Berger, U.S. Provisional Patent Application Ser. No.61/975,469, titled “COMPACT MEMORY STRUCTURE INCLUDING TUNNELING DIODE,”filed on Apr. 4, 2014 (Attorney Docket No. 4089.001PV2); (3) Berger,U.S. Provisional Patent Application Ser. No. 61/984,492, titled “COMPACTMEMORY STRUCTURE INCLUDING TUNNELING DIODE,” filed on Apr. 25, 2014(Attorney Docket No. 4089.001PV3); and (4) Berger, U.S. ProvisionalPatent Application Ser. No. 62/048,526, titled “COMPACT MEMORY STRUCTUREINCLUDING TUNNELING DIODE,” filed on Sep. 10, 2014 (Attorney Docket No.4089.001PV4); the entirety of each of which is hereby incorporated byreference herein.

BACKGROUND

Solid-state electronic memories are used widely across many hardwareplatforms, including embedded systems, mobile devices, desktopcomputers, and servers. Such memories can be classified in differentways, such as according to whether such memories are “volatile” or“non-volatile.” Generally, non-volatile memories can reliably retainstate after removal of input power. Conversely, volatile memoriesgenerally retain their state only when powered. In particular, volatilememories can be sub-classified as either static or dynamic. A staticmemory generally retains its state indefinitely when powered. Bycontrast, a dynamic memory may slowly lose its state, such as due toleakage of a storage structure within the dynamic memory. Accordingly,dynamic memories are generally “refreshed” in a manner where the stateof the memory is read and then written back to the storage structure inorder to preserve state.

Despite the inconvenience of refresh, dynamic random access memories(DRAM) have achieved tremendous adoption due to the ability to fabricateextremely dense arrays of such memories using relatively simple memorycell structures. For example, a single bit DRAM cell can be fabricatedusing as little as a single transistor and a single storage structure(e.g., a capacitor). FIG. 1A illustrates a simple schematicrepresentation of a one-transistor one-capacitor (1T-1C) DRAM cell 100A.FIGS. 1B, 1C, 1D, 1E, 1F, and 1G illustrate generally a variety of 1T-1CDRAM structures 100B, 100C, 100D, 100E, 100F, and 100G that can befabricated using semiconductor processing techniques, such as using asilicon complementary-metal-oxide-semiconductor (CMOS) process. FIGS. 1Athrough 1G can each include a bit line (BL) node 108, a word line (WL)node 106, a storage node 102, and a plate node 104. As transistorgeometries have shrunk, area inefficient planar capacitor structures,such as shown in FIG. 1B, have given way to a variety of other capacitorgeometries. Such geometries include more efficient stackedconfigurations (e.g., FIG. 1C), horizontally-finned or concentriccylindrical structures (e.g., FIGS. 1D and 1E), or trenchedconfigurations (e.g., FIGS. 1F and 1G).

FIGS. 2A, 2B, 2C, 2D, 2E, and 2F illustrate generally a series offabrication operations 200A, 200B, 200C, 200D, 200E, and 200F that canbe used to provide a concentric cylindrical capacitor configuration,such as similar to FIG. 1E. While the configurations shown in FIGS. 1Bthrough 1G and FIGS. 2A through 2F have increased area efficiency ascompared to first-generation planar structures, scaling limits mayexist. Such capacitor structures have also been enhanced by inclusion ofa high-relative-dielectric-constant (e.g., “high-x”) material, such as afilm, as a portion of a plate of the capacitor structure. Such materialscan include Ta₂O₅, Al₂O₃, or HfO₂. Such techniques have enabledsingle-die DRAM devices to achieve densities providing a gigabit (e.g.,about 10⁹ bits) of storage in a single device. By contrast, FIG. 3illustrates a schematic representation of a six-transistor (6T) staticrandom access memory (SRAM) cell 300. Such an SRAM cell 300 can offeradvantages of low latency, and a lack of requiring refresh (e.g., SRAMcan be referred to as “refresh-free”), but at a cost of significantlyhigher bit-cell complexity. In FIG. 3, transistors M1, M2, M3, and M4can provide a cross-coupled inverter pair configuration. Transistors M6and M5 can be controlled using a word line (WL), such as to couple thecross-coupled inverter pairs to a bit line (BL) and an inverted bit line(e.g., BL Bar or “BLB”).

Overview

The present inventor has recognized, among other things, that asemiconductor device exhibiting negative differential resistance (NDR)can be used instead of, or in addition to, a capacitor in a memory bitcell. In an example, an active load (e.g., a transistor-based load) canbe used along with tunneling devices exhibiting NDR to provide a memorystructure having a footprint comparable to a 1T-1C DRAM cell, butwithout requiring a periodic refresh to maintain a bit state whilepowered. Moreover, a series of NDR devices can be cascaded, such as toprovide a multi-bit memory cell having a footprint comparable to asingle-bit cell, such as by physically stacking the NDR devices. In anexample, one or more tunneling devices can be configured to provide asubstantially symmetric current-voltage relationship when biasedpositively or negatively with respect to a reference voltage. Such asymmetric current-voltage relationship can include negative differentialresistance regions in the both the positive and negative bias regimes,such as to support desired memory cell latching behavior.

In an example, a separate capacitor structure can be included in thememory cell structure, such as to provide enhanced drive capability. Forexample, a multi-bit cell having multiple tunneling devices can besupported by a single capacitor structure (such as a capacitor topologysimilar to a DRAM cell), providing enhanced density as compared to a1T-1C DRAM structure, and without requiring refresh, unlike the DRAMstructure. In an illustrative example, a symmetric tunneling device caninclude resonant inter-band tunnel diode (RITD) structures. An RITDstructure can be fabricated using semiconductor processing similar tothat used for Complementary Metal-Oxide-Semiconductor (CMOS) devicefabrication, such as including silicon. Multiple RITD structures can bestacked, such as to provide a desired symmetric NDR behavior asmentioned above and elsewhere.

Heterogeneous or alloy material combinations can be included as aportion of one or more RITD structures, such as can include, forexample, Silicon, Germanium, Carbon, Tin, or combinations thereof. Theexamples herein can be applied, for example, to stand-alone memorytechnology devices, or co-integrated with logic, such as for use as ahigh-speed cache or memory in a processor circuit or System-on-Chip(SoC).

This overview is intended to provide an overview of subject matter ofthe present patent application. It is not intended to provide anexclusive or exhaustive explanation of the invention. The detaileddescription is included to provide further information about the presentpatent application.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, which are not necessarily drawn to scale, like numeralsmay describe similar components in different views. Like numerals havingdifferent letter suffixes may represent different instances of similarcomponents. The drawings illustrate generally, by way of example, butnot by way of limitation, various embodiments discussed in the presentdocument.

FIGS. 1A, 1B, 1C, 1D, 1E, 1F, and 1G illustrate generally a variety of1T-1C DRAM configurations.

FIGS. 2A, 2B, 2C, 2D, 2E, and 2F illustrate generally a series offabrication operations that can be used to provide a concentriccylindrical capacitor configuration, such as similar to FIG. 1E.

FIG. 3 illustrates a schematic representation of a six-transistor (6T)static random access memory (SRAM) cell.

FIG. 4 illustrates generally a generic memory cell structure, such ascan include a tunneling device having negative differential resistance(NDR). Latch points for various drive configurations are shownillustratively below in

FIGS. 5A, 5B, and 5C illustrate generally latch points for various driveconfigurations, such as can be shown using respective load lines plottedon top of respective current-voltage (I-V) curves, where the I-V curvesexhibit NDR.

FIG. 6A illustrates generally an illustrative example that can include asingle bit cell comprising two or more semiconductor device structureshaving NDR.

FIG. 6B illustrates generally an illustrative example that can include aview of an integrated circuit layout corresponding to the schematicrepresentation of FIG. 6A.

FIG. 7A illustrates generally an illustrative example of a “hybrid”memory cell, such as including one or more device structures exhibitingNDR, a transistor structure as a transmission, and a capacitorstructure.

FIG. 7B illustrates generally an illustrative example that can include aview of an integrated circuit layout corresponding to the schematicrepresentation of FIG. 7A.

FIGS. 8A and 8B illustrate generally illustrative examples of multi-bitcells, such as can include multiple tunneling devices that can be one ormore of physically or electrically stacked.

FIG. 8C illustrates generally an illustrative example that can include aview of an integrated circuit layout corresponding to the schematicrepresentation of FIG. 8B.

FIGS. 8D and 8E illustrate generally latch points for multi-bitexamples.

FIG. 9 illustrates generally an illustrative example of athree-transistor two-tunnel-diode (3T-2TD) memory cell having a “gaincell” topology.

FIG. 10A illustrates generally a side view of a planar CMOS transistorstructure (e.g., a FET).

FIGS. 10B and 10C illustrate generally side views of CMOS transistorstructures, such as can include FinFET structures.

FIGS. 11A and 11B illustrate generally illustrative examples ofcurrent-voltage relationships that can be provided by respectiveresonant interband tunneling diode (RITD) structures.

FIGS. 12A and 12B illustrate generally illustrative examples of layerconfigurations for RITD structures, such as can provide thecurrent-voltage relationships shown illustratively in FIGS. 11A and 11B,respectively.

FIG. 13 illustrates generally an illustratively example of a “symmetric”current-voltage relationship, such as can be provided by an RITDstructure including two tunneling devices.

FIG. 14 illustrates generally an illustrative example of a p-n-p RITDstructure that can be implemented in silicon.

FIG. 15A illustrates generally an illustrative example of an n-on-p RITDstack-up that can include a Si/Ge “cladding” layer, with a tunnelbarrier formed by undoped Si and SiGe layers.

FIG. 15B illustrates generally an illustrative example of a calculatedband diagram corresponding to the stack-up shown illustratively in FIG.15A.

FIG. 16 illustrates generally an illustrative example of a Si/SiGe p-n-pstacked RITD structure including Si/Ge cladding.

FIG. 17 illustrates generally an illustrative example of a Si/SiGe n-p-nstacked RITD structure including Si/Ge cladding.

FIG. 18 illustrates generally an illustrative example of a generalizeddevice configuration.

FIG. 19 illustrates generally an illustrative example of anothergeneralized device configuration.

FIG. 20 illustrates generally an example of a generic Si-based RITDdesign, and a corresponding vertically stacked RITD pair using an npnpconfiguration of two generic Si-based RITDs connected serially by abackwards diode to generate a double NDR region.

DETAILED DESCRIPTION

As CMOS device dimensions become smaller, quantum and small-scaleeffects increasingly dominate and may limit further enhancement to CMOStechnology. For example, gate oxide tunneling, dopant or other localizedfluctuation, or channel quantization effects can limit scalability andperformance of CMOS technology. Accordingly, the present inventor hasrecognized, among other things, that device structures exhibitingnegative differential resistance (NDR), such as tunneling devices, canbe integrated with generally-available CMOS processing technology, suchas to enhance the performance of CMOS devices or to provide hybriddevices including both generally-available CMOS device structures alongwith tunneling device structures. In particular, such “hybrid” devicescan be used to realize area-efficient memory cell structures. Drivecurrent limitations of tunneling device structures can be addressed byusing capacitor structures coupled to the tunneling device structures.In this manner, latching behavior and a capacitive storage contributioncan be provided by the tunneling device structure. The tunneling devicestructure, in concert with a separate storage capacitor, can provideboosted drive current capability as compared to a stand-alone tunnelingdevice.

Tunnel diodes can be grouped into two general classifications. Intrabandtunnel diodes, which include resonant tunneling diodes (RTD), generallyexhibit NDR in both forward and reverse bias conditions, thus allowingtwo back-to-back RTDs to form a latch structure taking advantage of the“symmetric” NDR characteristics of each of the RTDs. Such RTDs can beused in memory cell examples herein. By contrast, interband tunneldiodes, which include resonant interband tunneling diodes (RITD),exhibit NDR only in the forward bias condition. Thus, to form thespecified back-to-back NDR latch, four RITDs, comprised of two pairs ofRITDs can be serially connected back-to-back and connected in betweenwith a low resistance p-n junction undergoing Zener tunneling at zeroreverse bias (e.g., as a backwards diode). This connective p-n junctionbetween the pairs of RITD structures does not require NDR in forwardbias, although it could exhibit such NDR behavior. This connective p-njunction can also be used to address a polarity mismatch of thesuccessive junctions used elsewhere for the RITD structures.

Integrated Memory Cell Structures

FIG. 4 illustrates generally a generic memory cell structure 400, suchas can include a tunneling device having negative differentialresistance (NDR). In an example, a driver tunnel diode TD_(D) can beconnected to a storage node (SN) 402 having a voltage represented byV_(SN). A load can be connected to the storage node. The load caninclude another NDR device such as a tunnel diode; a resistive load; oran active load such as a field-effect transistor (FET). A write accesstransistor MNO can be controlled such as using a wordline (WL) coupledto a gate of the transistor MNO. The transistor can then couple thestorage node 402 to a bitline (BL). A parasitic capacitance C_(D)intrinsic to the tunnel diode can be established by one of the tunneldevices, such as to provide storage of a bit state (or to provide atleast a portion of such storage as discussed in relation to otherexamples herein). The present inventor has recognized, among otherthings, that challenge can exist if such an intrinsic C_(D) capacitanceis insufficient to store or maintain a desired state. Accordingly, thepresent inventor has also recognized that the intrinsic C_(D)capacitance can be augmented with an explicit capacitor, such as in atrench or stacked configuration, added in parallel with the driver. Thedriver can include a single negative differential resistance device, ormultiple negative differential devices stacked or serially connectedelectrically.

FIGS. 5A, 5B, and 5C illustrate generally latch points (e.g.,corresponding to voltages V_(L) and V_(H)) for various driveconfigurations, such as can be shown using respective load lines 504,506, or 508 plotted on top of respective current-voltage (I-V) curves502, where the I-V curves 502 exhibit NDR. For example, in FIG. 5A, aplot 500A includes a resistive load line 504. In FIG. 5B, a plot 500Bincludes a transistor driver load line 506 (e.g., such as correspondingto a FET). In FIG. 5C, a plot 500C includes a tunnel diode loadcharacteristic 508 and a tunnel diode driver I-V curve 502. In eachcase, corresponding charging current (I_(SO)) and discharging current(I_(SI)) are also shown. The illustrations of FIGS. 5A, 5B, and 5C candescribe operation of a generic memory cell topology 400 such as shownin FIG. 4.

FIG. 5C illustrates generally that a combination of a tunnel diode load(TD_(L)) and tunnel diode driver (TD_(D)) can provide significant I_(SO)and I_(SI) magnitudes. For example, with a pair of tunneling devices,two latch points can be supported, such as a logic “0” in the region ofless than about 0.1V (e.g., before peak tunneling current), and a logic“1” near a valley of the tunneling current at about 0.4V. In thismanner, an operating voltage range can be established below 0.5V, suchas with a voltage swing of about 0.33V, fully integrated with CMOSdevices elsewhere on a commonly-shared integrated circuit. Such a lowoperating voltage swing, and high area efficiency generally illustratetunneling structure (e.g., RITD) desirability, such as for use in amemory cell. While the example above refers to using two states, othernumbers of states can be used. For example, tri-state, quad-state, oreven penta-state configurations can be used, such as using a 0.5V supplyrange for the first two states and roughly 0.5V for each additionalstate. As a number of states increases, a decrease in noise immunity ornoise-related instability may result. Examples of multi-bit celltopologies are illustrated generally in FIGS. 8A through 8C.

FIG. 6A illustrates generally an illustrative example 600 that caninclude a single bit cell comprising two or more semiconductor devicestructures having NDR and FIG. 6B illustrates generally an illustrativeexample 600 that can include a view of an integrated circuit layoutcorresponding to the schematic representation of FIG. 6A.

In an example, a memory cell (e.g., a random access memory (RAM) cell)can be fabricated to include two or more semiconductor device structureshaving a negative differential resistance (NDR), such as to provide asingle-bit or multi-bit memory cell. A single bit cell is shownillustratively in the examples 600 of FIGS. 6A (schematic) and 6B (e.g.,an overhead view of an integrated circuit memory cell layout). Asdiscussed elsewhere herein, a pair of negative differential resistancedevices (shown schematically as diodes) can be arranged back-to-back toform a latch. Each of the diodes TD_(L) and TD_(D) can include asubstantially symmetric current-to-voltage relationship. For example,the TD_(L) device and the TD_(D) device can each include a pair of RITDdevices to provide such symmetry. As mentioned above, a parasiticcapacitance can be provided as a portion of one of the tunnel devices,such as to provide storage of a bit state (or to provide at least aportion of such storage as discussed in relation to other examplesherein). Such storage can be augmented or even provided primarily by an“external” capacitor (e.g., an integrated capacitor providing acapacitance separate from a parasitic capacitance of the tunnelingdevice).

The cell of FIGS. 6A and 6B (e.g., a one-transistor two-tunnel-diode or1T-2TD cell) can use a DRAM-like read/write topology (e.g., such as caninclude a transistor MNO having an input coupled to a word line (WL),and having a bit line (BL) for transfer of charge between a storage node602 (e.g., using a capacitance provided by TD_(D)) and the bit line, orusing an “external” capacitor. Without being bound by theory, a 1T-2TDcell is expected to consume about 50% less power than a 1.2V 1T-1C DRAMcell, because the 1T-2TD cell can operate using a voltage swing of lessthan 0.5V if implemented using RITD devices. Similarly, if 1T-2TD isused as a replacement for an SRAM configuration, a power savings of 4.7times or more can be achieved, along with about a 6-fold reduction inarea, if using RITD devices to provide NDR.

FIG. 7A illustrates generally an illustrative example 700 of a “hybrid”memory cell, such as including one or more device structures exhibitingNDR, a transistor structure as a transmission, and a capacitorstructure. FIG. 7B illustrates generally an illustrative example 700that can include a view of an integrated circuit layout corresponding tothe schematic representation of FIG. 7A.

The example 700 of FIGS. 7A and 7B can include one or more devicestructures exhibiting NDR (e.g., tunneling devices), a transistorstructure MNO as a transmission gate (e.g., “write access transistor”),and a capacitor structure CAP, such as including an integrated capacitorconfiguration similar to one or more of the generally-available dynamicRAM (DRAM) capacitor structures discussed above. Such a memory cell asshown schematically in FIG. 7A (and as shown illustratively in thelayout of FIG. 7B), need not require refresh. A memory structureincluding NDR structures as shown can retain state when powered, withoutrequiring refresh, eliminating refresh latency and offeringcharacteristics more similar to SRAM while having a DRAM-like footprint.

In the example 700 of FIG. 7A (or other examples), a capacitor generallyused for DRAM fabrication, either trench or stacked, for example, can beconnected in an electrically parallel configuration with one of the NDRdevices. A self-restoring current of the NDR pair can hold a voltagestored on the capacitor (e.g., a bit value), providing refresh-freestorage. A tunnel device can provide such NDR and is simple and compact.In an illustrative example, tunnel devices can be vertically stackedupon or nearby a transistor structure, such as to provide enhancement tocell compactness as compared to generally-available DRAM memory cellstructures. For example, a load tunnel diode and a driver tunnel diodecan be fabricated directly upon a transistor source or drain region, asdiscussed in various examples below.

If the tunnel devices include RITDs, a standby current density and drivecurrent density, or an RITD Peak-to-Valley Current Ratio (PVCR) may beinsufficient to meet a desired level of power efficiency or performance.The present inventor has recognized, among other things, that the 1T-2TDexample 600 of FIGS. 6A and 6B can be modified, such as to provide the“hybrid” cell example 700 of FIGS. 7A and 7B, including a capacitor CAP(e.g., an integrated capacitor similar in architecture to capacitorsused generally in DRAM cell configurations) separate from the parasiticcapacitance provided by the RITD.

In an illustrative example, a standby leakage current density criterioncan be on the order of about 6 milliamps per square centimeter (mA/cm²).RITD structures have been fabricated having peak current densities aslow as 20 mA/cm², and accordingly a valley current below a 6 mA/cm²threshold is feasible. However, a minimum drive current criterion canalso be stringent, such as on the order of greater than 0.4 megaamps persquare centimeter (MA/cm²). RITD structures have been fabricated havingpeak current densities higher than 0.2 MA/cm². The present inventor hasrecognized that such high drive current need not be provided exclusivelyby an RITD.

For example, as shown in FIGS. 7A and 7B, an integrated capacitor CAP(such as using a capacitor structure similar to capacitors generallyused for CMOS DRAM structures) can be used, such as in a parallelconfiguration with one or more TDs, or otherwise connected to acommonly-shared storage node 702 along with one or more TDs. Size andarea savings can still be achieved using one or more RITDs because a TDcapacitance can contribute to the storage capacitance of the cell, sothe integrated capacitor separate from the TD can have a lowercapacitance as compared to an example lacking a TD. A standby current ofthe structure illustrated in FIG. 7A can be about 0.043 times anormalized standby current of a 1T-1C DRAM cell, with an area and drivecurrent comparable to a 1T-1C DRAM cell, while providing a benefit ofnot requiring refresh. The structure shown in FIG. 7A also reduces oreliminates a need for a large PVCR in the TD devices.

Other techniques can be used to further enhance area efficiency of amemory cell including a tunneling device. For example, FIGS. 6A through6B and 7A through 7B illustrate generally a single-bit cell topology. Amulti-bit cell can be formed, such as using multiple tunneling devicesthat can be one or more of physically or electrically stacked, such asshown in the examples of FIGS. 8A through 8E.

FIGS. 8A and 8B illustrate generally illustrative examples 800A and 800Bof multi-bit cells, such as can include multiple tunneling devices thatcan be one or more of physically or electrically stacked. In FIG. 8A, astack of devices TD_(D) having NDR can be arranged to store respectivebits. Such devices having a substantially symmetric NDR (e.g., such asserially-connected RITDs) can be fabricated in a physically-stackedconfiguration having an area comparable to the single-bit 1C-2TDstructure of the example 700 of FIGS. 7A and 7B, but providingadditional storage bits. In this manner, a normalized area of amulti-bit cell can be a fraction of the corresponding area consumed by a1T-1C DRAM cell (e.g., a structure having 4 bits of storage wouldconsume only about 0.35 times the area of a 1C-TC DRAM, per bit, and an8-bit structure would consume only about 0.17 times the area of the1C-TC DRAM, per bit). In the example of FIG. 8A or 8B, read or writeoperations can be performed serially such as using a write accesstransistor MNO controlled by a wordline (WL) to couple a bitline (BL) toa storage node 802. The present inventor has recognized, among otherthings, that increasing density by using multiple stacked tunnelingstructures can provide scale reduction in a manner that is moreefficient than attempting to scale down an integrated capacitor of aDRAM cell in the absence of using tunneling devices.

In an example 800B, such as shown illustratively in FIG. 8B, a loaddevice (e.g., TD_(L) as shown in FIG. 8A) can be replaced with an activeload MNL, such as including a FET device (e.g., ametal-oxide-semiconductor FET device), labeled “Load.” A correspondingintegrated circuit layout of the example 800B is shown illustratively inFIG. 8C. In another example, a three-terminal RITD device (e.g., a“Tunnel FET”) can be used in place of the MOS transistor, and cansimilarly operate using a compressed voltage swing of less than 0.5V perNDR driver element, such as to provide an overall reduction of powerconsumption of about 80% versus a 1T-1C DRAM cell. Similarly, a powersavings of about 25% would be expected in comparison to an 0.8V DRAMcell, if 1T-2RITD cell topology is used, and about 50% if a TFET is usedin place of a MOS transistor.

RITD structures, in contrast with Esaki tunneling structures, do notgenerally require complex alloy processing. Also, RITD structures, incontrast with other resonant tunneling diode structures, do notgenerally require large conduction band offsets. For example, use ofSi/SiGe materials in an RTD (as compared to an RITD), would generallyinclude using a thick relaxed buffer layer to strain engineer asignificant enough conduction band offset to create manifest quantumconfinement. As discussed further in other examples herein, one or moreRITDs can be fabricated in a vertically-stacked configuration, so theexamples discussed above can include using a structure having RITDsfabricated in a stacked configuration. The examples described herein aregenerally compatible with a variety of processes, integrated capacitor,and integrated transistor device structures such as are generallyassociated with CMOS fabrication.

For example, RITD structures such as shown and described herein can beco-integrated with other silicon-based devices, such as can includedigital CMOS transistor circuits at 90 nanometer (nm), 65 nm, 45 nm, 32nm, 22 nm, 14 nm, or 10 nm process nodes, or beyond. Such process nodescan include use of strained-silicon device configurations, high-κdielectrics, metal gate structures, or other device structures such asmulti-gate structures. RITD structures can be fabricated at least inpart using thin epitaxial CVD growth, such as to provide an activeregion about 8 nm thick. In an example, an RITD can be grownsequentially atop SiGe source and drain regions, showing that RITDprocessing can be easily integrated with planar CMOS fabrication flow.

For multi-valued bit cells such as shown illustratively in FIGS. 8Athrough 8C, tunnel diodes can be vertically stacked for compactness. Forexamples including interband tunnel diodes, this creates a polaritymismatch by generating a reverse biased parasitic p-n junction. But, byestablishing the appropriate adjoining polarity types, a backward diodecan be formed that is actually operating in Zener reverse bias. In thismanner, multiple RITDs can be cascaded serially providing multiple NDRregions.

FIGS. 8D and 8E illustrate generally latch points for the multi-bitexamples. As an illustrative example, a 1T-1C-3TD cell can be formedusing three serially connected tunnel diodes as the driver with a secondtransistor (separate from the word line gate) being used as the load,such as shown in the example 800B of FIG. 8B. The three seriallyconnected tunnel diodes TD_(D) can provide three negative differentialresistance regions. However, as shown illustratively in the I-V plot800C of FIG. 8D, the load transistor (or a resistor or other suitabledevice) manifests with four stable intersection latch points where theload line 804 intersects the stacked tunnel diode I-V curve 806A“humps,” thus providing a 4-bit storage cell topology. FIG. 8E extendsthis to serially connect seven tunnel diodes to create seven negativedifferential resistance regions. As shown illustratively in the plot800D similar load line analysis provides for eight stable latch pointsat the intersection between the transistor load line 804 and the I-Vcurve 806B of the tunnel diode stack, thus enabling a compact 1T-1C-7TD8-bit cell.

Other memory cell topologies can be used. For example, FIG. 9illustrates generally an illustrative example 900 of a three-transistortwo-tunnel-diode (3T-2TD) memory cell having a “gain cell” topology. Thetunnel diodes TD_(L) and TD_(D) can be symmetric, as in other examplesdescribed herein. For example, each of TD_(L) and TD_(D) can include apair of back-to-back interband tunnel devices to provide a symmetrictunnel diode device. The back-to-back tunnel devices can be coupledtogether using a backward-connected diode (e.g., a pn junction can beestablished at the interface between back-to-back tunnel device, such asa pn junction configured to operate in a reverse breakdown region asmention in other examples). The gain-cell topology can include a writeaccess transistor MNO controlled by a wordline (WL) to couple a bitline(BL) to a storage node 902, along with a read transistor MN1 coupled toa read access transistor MN2, the read access transistor MN2 controlledby a readline.

FIG. 10A illustrates generally a section view of a planar CMOStransistor structure 1000A (e.g., a FET). The Si/Ge regions can definedrain or source regions (D/S), and conduction through the transistor canbe controlled using a gate region (G). A high-κ dielectric film can beincluded as a portion of the gate structure, such as just above achannel region between the drain or source regions (D/S). One or moretunnel devices (TD) can be fabricated, such as upon a Si/Ge drain orsource region (D/S) as shown in FIG. 10A. In this manner, varioustunneling device structures or stacks of such structures can befabricated in a highly-integrated fashion compatible with other CMOSprocessing. For example, the one or more RITD devices can be fabricatedin the source or drain regions such using a device structure as shown inone or more of the examples of FIGS. 11A through 11B or 12A through 12B,or other examples, such as to provide a substantially symmetric NDRdevice for use as a portion of a memory cell.

FIGS. 10B and 10C illustrate generally side views of CMOS transistorstructures 1000A and 1000B, such as can include FinFET structures.

In an illustrative example, a fin Field Effect Transistor (finFET) caninclude conformal doping along a raised fin used as a portion of thesource or drain structure of the finFET. CVD processing used tofabricate the finFET can be similar to the CVD processing used to forman RITD. In an example where the RITD 15 connected serially to a drainstructure of a transistor (e.g., a drain portion of a finFET), conformalgrowth of the RITD allows the RITD to be directly connected to thefinFET to provide a highly-compact footprint. Examples of side sectionviews (with gate structure penetrating into or out of a plane of thedrawing page) of finFET device structures 1000A and 1000B are shownillustratively in FIGS. 10B and 10C and are labeled similarly to theexample of FIG. 10A.

Illustrative Examples of RITD Structures and Techniques for FabricatingRITD Structures

FIG. 11A and FIG. 11B show illustrative examples of current-voltagerelationships 1100A and 1100B that can be provided by respective RITDstructures, such as having processing and geometric conditions as showninset in the plots of FIGS. 11A and 11B.

FIGS. 12A and 12B illustrate generally illustrative examples of layerconfigurations for RITD structures, such as can provide thecurrent-voltage relationships shown illustratively in FIGS. 11A and 11B,respectively. A single n-on-p RITD structure implemented on silicon caninclude a stack-up similar to FIG. 12A to provide an I-V characteristic1100A as shown in FIG. 11A. Because quantum mechanical tunnelingprobability, and therefore the correlated tunneling current density, isexponentially related to tunneling distance, the spacing between thedegenerate doping zones generally determines this value. For thedelta-doped RITDs illustrated in FIGS. 12A and 12B, this tunnelingdistance is given by L and L1+L2, respectively. A tunneling distanceneeded for the specific circuit application can be selected byspecifying L and L1+L2 appropriately.

A single p-on-n RITD structure implemented on silicon can include astack-up similar to FIG. 12B to provide an I-V characteristic 1100B asshown in FIG. 11B. The characteristics 11A and 11B can be referred to as“asymmetric,” because such characteristics only show an “N”-shapednegative differential resistance behavior in a single quadrant of theI-V plot. In FIG. 11A, the NDR behavior appears in a positively-biasedcondition in quadrant (I), and in FIG. 11B, the NDR behavior appears inthe negatively-biased condition in quadrant (III). RITD structures cangenerally provide a peak-to-valley current ratio (PVCR) of up to 5.2, inan illustrative example. According to simulation and analysis, valleycurrent can be determined at least in part by defect current.Illustrative examples of device structures fabricated in laboratoryconditions have exhibited acceptable thermal stability of up to 200degrees C. and beyond, invariant to burn-in, and have shown immunity toradiation exposure.

FIG. 13 illustrates generally an illustratively example of a “symmetric”current-voltage relationship, such as can be provided by an RITDstructure including two tunneling devices. The present inventor hasrecognized among other things that RITD structures can be stacked, suchas to provide a symmetric current-voltage relationship as shownillustratively in FIG. 13. The I-V characteristic 1300 shown in FIG. 13can be said to be substantially symmetric. In this sense, the structureneed not exhibit a literal “mirror image” symmetry, but correspondingNDR behaviors are exhibited in both quadrants (I) and (III).

For example, FIG. 14 illustrates generally an illustrative example of a“stacked” p-n-p RITD structure 1400 that can be implemented in silicon,such as to provide a symmetric current-voltage relationship. FIG. 15Aillustrates generally an n-on-p RITD stack-up that can include a Si/Ge“cladding” layer, with a tunnel barrier formed by the undoped Si andSiGe layers. By judicious placement of SiGe surrounding the boron (B)delta-doping (δ-doping plane) on both sides, a valence band quantum wellis not only preserved, but enhanced. FIG. 15A shows an illustrativeexample 1500A of a high quality delta-doped RITD with a 6 nm tunnelingspacer. The calculated band diagram 1500B of FIG. 15B corresponding tothe structure of FIG. 15A clearly indicates the creation of conductionand valence band quantum wells established by effective delta-doping. Inan illustrative example, for the structure shown in FIG. 15A, L1 can be2 nm, and L2 can be 4 nm.

In applications involving memory cell structures, to achieve cellcompactness, epitaxially-fabricated tunnel diodes, such as includingRITD structures, can be stacked as a p-n-p or n-p-n configuration. Forexample, a forward bias of a driver RITD and a reverse bias of a loadRITD will overlap to form a back-to-back tunnel diode latch (see, e.g.,FIG. 5C showing such overlapping responses). Depending upon the hybridtunneling RAM cell layout, two back-to-back NDR devices (e.g., eachincluding two RITDs to provide symmetric I-V behavior) can beepitaxially defined in separate locations atop a MOS transistor, such asusing the source/drain contact as the central “sense” node. In this way,the two NDR devices will be biased oppositely, so that a forward biasedNDR region (e.g., of a first interband tunnel diode) intersects anotherforward biased NDR region (e.g., of a second, inverted, interband tunneldiode). As mentioned above, for examples including RITD devices, eachNDR circuit branch can include a pair of RITD devices to providesymmetry. Accordingly, an individual (e.g. “asymmetric”) RITD device ina particular branch that is reverse biased simply acts as a shortcircuit, and thereby effectively disappears from the circuit when in areverse-biased state.

A delta-doped (6-doped) RITD can be used as a “building block” deviceelement. Such delta-doped RITD structures can be stitched together toprovide the back-to-back interband tunnel diode stack. For example, twoback-to-back RITDs can have a p-n-p or n-p-n configuration such asdepending upon a conduction type of the transistor on whose source ordrain region the stack can be fabricated. For an NMOS conduction type,an n-p-n RITD stack can make co-integration more seamless withoutintroducing an additional energy barrier. Similarly, for a PMOSconduction type, a p-n-p tunnel diode configuration can be used.

Other pairing can also be co-integrated (e.g., p-n-p on NMOS or n-p-n onPMOS), such as by the integration of a Zener tunneling reverse-biasedp-n tunneling junction (e.g., a backward diode) located at the interfacewhere there would otherwise be a polarity mismatch. Synthesizingback-to-back interband tunnel diodes as specified above, particularlythe p-n-p or n-p-n RITDs, generally involves careful control of dopantincorporation, controlling both diffusion and segregation. Tunnel diodesrequire doping to exceed the degeneracy condition to manifest theirnegative differential resistance behavior. Generally, doping well above10¹⁹ cm⁻³, and even up to and beyond 10²⁰ cm⁻³, concentration is used tomeet such a degeneracy condition. In order to suppress deleteriouseffects caused by dopant redistribution, which can lower the dopinglevels below the degeneracy condition needed for quantum tunneling,epitaxial growth conditions are carefully controlled.

For example, where molecular beam epitaxial growth (MBE) is used forfabrication, dopant segregation can be reduced or minimized such as bylowering the substrate temperature during growth of those doping layersthat require the degeneracy condition for quantum tunneling, forinstance delta-doping in the RITDs, thereby preventing theirincorporation into the doped overlayers above in a multi-layer RITDstack. Such incorporation can undesirably lead to counter dopingconsequences. Counter doping can lead to compensation which lowers theeffective doping level below the degeneracy condition, rendering theoverlaying tunneling devices inoperative. Further, the energy statesassociated with compensation as well as crystalline vacancies triggeredby low adatom mobility on the substrate lead to defect mediatedtunneling through the forbidden bandgap. This also lowers the tunnelingdevice performance by reducing the quantum selection rules, thus thepeak to valley current ratio will typically reduce. Either a lowering ofthe substrate temperature during MBE epitaxial growth to a level that istoo low, or lower than nominal for too long can both contribute to poorepitaxial quality, so care is generally exercised to selectively reducethe substrate temperature during the problematic layers (e.g., thosetargeted to meet the degeneracy condition) only. In an alternateapproach, chemical vapor deposition (CVD) can control dopant segregationthrough reactor pressure, such as toggling between reduced pressure andatmospheric pressure. With a hydrogen containing environment, elevatedchamber pressure is one element that suppresses segregation, allowingfor higher substrate temperatures during CVD epitaxial growth withoutthe concurrent production of vacancy defects that elevate the valleycurrent.

Generally, p-type dopants, such as boron, do not segregate as badly asn-type dopants, such as Sb, P, or As. So, it is generally the n-typelayer for which dopant segregation should be most carefully managed.Counter-intuitively, however, when epitaxially growing a p-layer of an-p-n interband tunnel diode stack or the top-most p-layer of a p-n-pinterband tunnel diode stack, enhancing segregation of the n-type dopantduring epitaxial deposition of the p-type film can improve deviceperformance, by effectively sweeping the excess n-type dopants throughthe p-doped region, thereby preventing their deleterious incorporation.

In an illustrative example, a thin layer of epitaxial growth can bedeposited under reduced segregation conditions, such as about 1 to about3 nanometers, to freeze in as much of the n-type dopants riding atop thegrowth front as possible and immediately surrounding the desirablen-type degeneracy region. Thereafter, the segregation can be enhanced soas to effectively sweep the n-type dopant past the p-type doping region,and through segregation effects, very few n-type dopants actually becomeincorporated into regions intended to be doped p-type. Thus, any excessn-type segregating dopants are removed from compensation or dopant pairdeep level formation and pushed away from the active tunneling junction.

Further augmentations can be used to improve the integrated RITDperformance, such as by strategically inserting thin Ge containingSi_(x)Ge_(1-x) layers, below a critical thickness, immediately claddingthe boron (B) delta-doping layers. Since boron is an interstitialdiffuser, the lattice strain imparted by the larger diameter Ge atoms,substitutionally replacing Si atoms, can serve to reduce theinterstitial vacancies, thereby inhibiting the B from outdiffusingduring subsequent thermal processing. As mentioned above, the presentinventor also recognizes that the RITDs co-integrated into the hybridDRAM cell can be tailored for the necessary current density needed byadjusting the effective tunneling distance, nominally set by thedistance between the p-type and n-type delta-doping planes.

FIG. 16 illustrates generally a Si/SiGe p-n-p stacked RITD structure1600 with Si/Ge cladding. In this illustration, the 1 nm n⁺ Siliconlayers and the 4 nm Si_(0.6)Ge_(0.4) alloy layers can be regarded as abasic configuration around which further variation can be made,principally to alloy composition and thickness of the 1 nm Si and 4 nmSiGe layers, respectively. For example, tunneling distances denoted by“Y” can then be set by a silicon layer thickness denoted by “X,” such asto establish a desired current density.

FIG. 17 illustrates generally a Si/SiGe n-p-n stacked RITD structure1700 with Si/Ge cladding. In this illustration, the 1 nm n⁺ Siliconlayers and the 4 nm Si_(0.6)Ge_(0.4) alloy layers can again be regardedas a basic configuration around which further variation can be made. Asin the example of FIG. 16, X can include a value of about 2 nm, or caninclude a range of values from about 0.5 nm to about 25 nm, or one ormore other ranges such as from about 1 nm to about 16 nm.

In an illustrative example including a hybrid memory cell application(such as discussed above), If an underlying base layer (e.g., substrate,diffusion or epilayer in a source or drain region of a transistor)incorporates SiGe, then a percentage of Ge in alloyed regions shown inFIG. 16 or 17 can be raised commensurately.

Other device configurations are possible, such as can include using awide range of materials. Silicon-based resonant interband tunnelingdiodes (RITD) generally exhibit a peak tunneling current that can becontrolled dominantly by the parameters that define the tunneling spacerof the RITD, set by a tunneling barrier bandgap and a tunnelingdistance. For delta-doped RITDs, the tunneling distance can beestablished using a distance between a respective p-type delta-dopingquantum well and a respective n-type delta-doping quantum well. Resonanttunneling occurs from the filled states of one quantum well to the emptystates of the other polarity quantum well.

An alloy composition of an RITD tunneling barrier can be used toestablish a specified bandgap, and a resulting tunneling probability.Current density is exponentially related to an energy barrier height. Inan example, a silicon-germanium-carbon-tin alloy can be used. Althoughthe Group IV material system defined by a SiGeCSn alloy system is notcompletely miscible over the full stoichiometric range, there are quitea number of permutations that are available that provide tailoring ofthe bandgap as well as strain control. SiGeCSn opens the door to a widevariety of Si-based heterostructure devices commonly reserved for III-Vcompound semiconductors. For example, SiGe clearly demonstrates improvedperformance as compared to non-compound or non-alloyed devicestructures. SiGe technology has become ubiquitous amongst the siliconmicroelectronics industry. However, SiGe is not lattice-matched tosilicon substrates. The silicon diamond lattice must accommodate alarger atomic diameter of Ge atoms and is distorted accordingly, bothlocally and on long range. Such strain deformation can be used tobeneficially modify a transistor channel band structure, therebyreducing the channel carrier effective mass.

By additions of Ge and C in a roughly 8:1 ratio, a SiGeC alloy canmaintain Si lattice matching. Similarly, Group IV alloys incorporatingthe larger atomic diameter of Sn could be compensated by the addition ofsmaller-diameter C atoms. By adding Sn to the diamond Group IV crystallattice, the bandgap can be reduced significantly. Further, binaryalloys of SiSn and GeSn may lead to quasi-direct bandgap materials thatwould avoid phonon-mediated band-to-band tunneling expected ingenerally-available SiGe materials.

Bypassing phonon-mediated tunneling could greatly enhance tunnelingprobability, allowing direct tunneling, and thereby improve tunnel diodeperformance, even facilitating tunneling over longer tunnelingdistances. Unlike Si and Ge, which mix well, the GeC binary systemshould not occur under equilibrium conditions, and SiC alloys want toprecipitate out as a carbide. Carbon, which has a much smaller latticeconstant and atomic radius is difficult to get incorporated into thecrystal lattice substitutionally. Much of the carbon enters the latticeinterstitially.

Without being bound by theory, Brillioun Zone folding by growing shortperiod superlattices could convert the SiGeC indirect bandgap to aquasi-direct bandgap. A new binary superlattice can be viewed as a newcrystal with a different Bravais lattice. Within the material, a newenergy state is created at the zone center by which efficient opticaltransitions can occur. Also, by tailoring the ternary alloy or buffercomposition, strain can be independently controlled about the latticematching condition for Si substrates. Strain can act to modify the bandstructure as well.

The present inventor has recognized that adding certain alloycompositions surrounding the p-type and n-type delta-doping layerscontributes to effectively cladding the delta-doping and suppressingdopant outdiffusion, such as in the illustrative example of using SiGearound p-type doping domains. The level of degeneracy and the density ofstates inside the n-type and p-type quantum wells also controls thequantum tunneling efficiency of RITDs. Larger quantum well carrierdensity and density-of-states both aide in RITD tunneling probabilityand performance leading to higher peak-to-valley current ratios and peakcurrent densities.

The present inventor has also recognized that C-doping can bestrategically applied to suppress p-type dopant outdiffusion,particularly in relation to boron-doped regions, for example. In anexample, without being bound by theory, directly adding C doping withinthe vicinity of the p-type delta-doping spike can lead to solutionhardening and inhibit the interstitial mediated diffusion common to Bdoping, and independent of Group IV alloy composition and bandgaptailoring, mentioned previously. Thus, a p-type delta-doping spike in aspecified region (e.g., an injector layer or confinement region) can beretained and can be more tolerant of subsequent high temperatureprocessing as well as extending tunnel diode device lifetime andlowering device dependency upon ambient temperature.

FIG. 18 illustrates generally an illustrative example of a generalizeddevice 1800 configuration, such as can be fabricated upon a region 1802such as substrate, an epitaxial layer, or upon a portion of anotherintegrated device structure such as a transistor. For example, theregion 1802 can include a diffusion or well region 1804. A first bufferlayer 1806 can include a semiconductor material such as silicon, acompound semiconductor, or an alloy such as a silicon-germanium alloy orother combination of materials. Such a buffer layer 1806 can provide abuffer between a first semiconductor layer 1808 having a firstconductivity type opposite a second conductivity type of the region 1802or well region 1804. A first quantum well 1840 can be formed such as byestablishing a first delta-doped region 1810 upon or within the firstsemiconductor layer 1808. The first delta-doped region 1810 can share afirst conductivity type with the first semiconductor layer, but can bedoped to a much higher concentration, such as to meet a degeneracycriterion, such as to provide a first “injector” layer. A spacer 1850can be formed such as using one or more regions formed upon thedelta-doped region 1810, such as to establish a tunneling barrier. Forexample, the first spacer 1850 can include an insulator or asemiconductor material, such as an intrinsic semiconductor, a compoundsemiconductor, or an alloy. The first spacer 1850 can include variouslayers having different materials or different doping concentrations,such as to provide a “composite” spacer.

A first portion 1812 of the first spacer 1850 can include an undopedintrinsic semiconductor such as silicon, such as in an illustrativeexample wherein the first conductivity type is n-type (e.g., wherephosphorus is used as a dopant) in the first delta-doped region 1810. Inthis illustrative example, a second portion 1814 of the first spacer1850 can include a semiconductor alloy, such as an alloy of silicon andgermanium to provide a first “cladding” layer adjacent to a seconddelta-doped region 1816. The second delta-doped region 1816 can have asecond conductivity type opposite the first delta-doped region 1810,such as a p-type region that can include boron doping at a concentrationmeeting a degeneracy criterion. The second delta-doped region 1816 canprovide a second “injector.”

A second spacer 1870 can be used to establish a second tunnelingbarrier. Similar to the first spacer 1850, the second spacer 1870 caninclude one or more layers that can include an insulator or asemiconductor material. In an example where the second delta-dopedregion 1816 includes a p-type conductivity (e.g., using boron), a secondportion 1818 of the second spacer 1870 can include a silicon-germaniumalloy such as to provide a second “cladding” region around the seconddelta-doped region 1816. Other materials or alloys can be used for such“cladding” regions, such as a SiGeCSn alloy, as discussed elsewhereherein.

A first portion 1820 of the second spacer 1870 can include an intrinsicsemiconductor or insulator, such as in an illustrative example where athird delta-doped region 1822 includes the first conductivity type(e.g., an n-type conductivity). The third delta-doped region 1822 canestablish a third quantum well 1880, such as to provide a third“injector” layer. A thickness of the first spacer 1850 can be used atleast in part to control a probability of carriers tunneling from thefirst quantum well 1840 to the second quantum well 1860, and a thicknessof the second spacer 1870 can be used at least in part to control aprobability of carriers tunneling from the second quantum well 1860 tothe third quantum well 1880. One or more layers can be formed on a faceof the third delta-doped region 1822 opposite the second spacer 1870.For example, one or more layers such as a second semiconductor layer1824 or a third semiconductor layer 1826 can be formed on the face ofthe third delta-doped region 1822 opposite the second spacer 1870.

As discussed elsewhere herein, processing under “low” or “high”segregation conditions can be used, such as to provide or maintain adesired doping concentration within one or more of the first, second,and third delta-doped regions 1810, 1816, and 1822. In an illustrativeexample where the first delta-doped region 1810 includes an n-typeconductivity, a low segregation processing condition can be used for thefirst portion 1812 of the spacer 1850. A high segregation processingcondition can be used for formation of one or more of the second portion1814 of the first spacer 1850. Similarly, where the third delta-dopedregion 1822 includes an n-type conductivity and where the secondsemiconductor layer 1824 includes an n-type conductivity, a lowsegregation processing condition can used during formation of the secondsemiconductor layer 1824. A high segregation processing condition can beused during formation of a third semiconductor layer 1826, alsoincluding an n-type conductivity. In this manner, an n-p-n interbandtunneling device stack can be formed, such as to provide a symmetricnegative differential resistance around a zero-bias condition (see,e.g., FIG. 17).

In another illustrative example, the first conductivity type can insteadbe a p-type conductivity (e.g., the first delta-doping region 1810 andthe third delta-doped region 1822 can include p-type conductivity). Thesecond delta-doped region 1816 can include n-type conductivity. Thefirst and second portions of each of the spacers 1850 and 1870 can beswapped, for example, so that in this example the semiconductor alloyregions of the spacers 1850 and 1870 are located in contact with thefirst delta-doped region 1810 (as in the case of the spacer 1850) andwith the second delta-doped region 1822 (as in the case of the spacer1870), respectively, to provide cladding of the p-type delta-dopedregions 1810 and 1822. In this illustrative example, the firstsemiconductor layer 1808 can also include a semiconductor alloy, such asdoped to provide a conductivity type (e.g., p-type) matching the firstdelta-doped region 1810, but at weak concentration in comparison to thedegenerate delta-doped “spike” of the delta-doped region 1810.Similarly, in this example, the second semiconductor layer 1824 caninclude a semiconductor alloy doped to provide a conductivity type(e.g., p-type) matching the third delta-doped region 1822. The locationswhere low and high segregation conditions can be used for the formingthe layers of the spacers 1850 and 1870 can be similarly swapped forthis example and in this manner a p-n-p interband tunneling device canbe formed (see, e.g., FIG. 16). The second or third semiconductor layers1824 or 1826 can provide an offset between a top contact and a topinjector (e.g., the third delta-doped region 1822).

The spacers 1850 and 1870 need not include exactly one or two layers.For example, FIG. 19 illustrates generally an illustrative example of ageneralized device 1900 configuration, such as can be fabricated upon asubstrate, an epitaxial layer, or upon a portion of another integrateddevice structure such as a transistor. In the example of FIG. 19, one ormore confinement layers can be separated from adjacent confinementlayers in a device stack such as using a “composite” barrier includingthree or more layers. For example, a substrate region 1902 can include awell region 1904 (or the other layers can be formed directly upon thesubstrate region 1902).

The device 1900 can include a first conductivity type layer 1908, and afirst confinement layer 1940 (e.g., a first delta-doped region 1910). Abuffer layer 1906 can be included between the first conductivity typelayer 1908 and the substrate 1902. A first tunneling barrier 1950 can beformed between the first confinement layer 1940 and a second confinementlayer 1960 (e.g., a second delta-doped region 1916). The secondconfinement layer 1960 can have a second conductivity type opposite thefirst confinement layer 1940. A second tunneling barrier 1970 can beformed next to the second confinement layer 1960 to separate the secondconfinement layer 1960 from a third confinement layer 1980. The thirdconfinement layer 1980 can include the first conductivity type.

The tunnel barriers 1950 and 1970 can include multiple layers. Forexample, the first spacer can include first and second low-doped spacerlayers 1912A and 1912B. A first tunneling layer 1914A can be formedbetween the first and second low-doped spacer layers 1912A and 1912C.Similarly, a second tunneling layer 1914B can be located between thirdand further low-doped spacer layers 1912C and 1912D. In an example, atleast one of the layers included in the first or second tunnelingbarriers 1950 and 1970 can include an intrinsic semiconductor material.Other materials can be included in one or more of the layers comprisingthe first and second tunneling barriers 1950 and 1970, such as aninsulator, a compound semiconductor, or a semiconductor alloy.

FIG. 20 illustrates generally an example of a generic Si-based RITDconfiguration 2000A, and a corresponding vertically stackedconfiguration 2000B including an RITD pair, such as can be included as aportion of a multi-state memory circuit providing multiple “humps” in acorresponding current-voltage response.

In the configuration 2000A, an n+ injector layer can be provided nearbyan n-type delta-doping plane (e.g., such as can be doped usingphosphorus). Undoped Si and Si_(x)Ge_(1-x) layers having thicknesses L₁and L₂ can be provided, such as between the n-type delta-doping planeand a p-type delta-doping plane (such as can be doped using boron). Acladding layer can be provided adjacent to the p-type delta-dopinglayer, such as can include a Si_(x)Ge_(1-x) layer having thickness L₃. Ap+ injector layer can be provided between the lower Si_(x)Ge_(1-x) layerand the substrate.

In the stacked configuration 2000B, the RITD pair can provide an npnpconfiguration of two generic Si-based RITDs (e.g., each includingdelta-doping and cladding as shown in the bracketed region of theconfiguration 2000A) connected serially by a backwards diode (e.g.,including n+ and p+ layers having thicknesses L₄ and L₅ respectively) togenerate a double NDR region. In this manner, the structure 2000B shownin FIG. 20 can provide three states. Further RITDs can be included inthe stacked configuration 2000B, such as coupled serially throughadditional diode structures similar to the L₄/L₅ layer pair, such as toprovide additional “humps” in the corresponding current-voltagecharacteristic, enabling additional states such as four, five, six,seven, or even more states. Such current-voltage relationships areillustrated generally in FIGS. 8D and 8E as illustrative examples (e.g.,a three RITD driver structure can provide a current-voltage responsesimilar to FIG. 8D and a seven RITD driver structure can provide acurrent-voltage response similar to FIG. 8E). The present inventor hasrecognized, among other things, that a configuration 2000B, such asshown in FIG. 20, can be coupled to an external capacitor (e.g., anintegrated capacitor other than a parasitic capacitor provided by one ormore tunnel diode structures), such as to provide a robust multi-statememory without requiring refresh.

Various Examples Including Device Structures and Fabrication Techniques

Example 1 can include or use subject matter (such as an apparatus, amethod, a means for performing acts, or a device readable mediumincluding instructions that, when performed by the device, can cause thedevice to perform acts), such as can include or use an electronicdevice, comprising an integrated circuit including an integratedtransistor, an integrated capacitor coupled to the integratedtransistor, a pair of devices each exhibiting symmetric negativedifferential resistance, where the integrated transistor, the integratedcapacitor, and the device pair are arranged to provide a memory cell,the memory cell configured to store a bit value at least in part using acapacitance provided by a portion of the pair of devices exhibitingsymmetric negative differential resistance.

Example 2 can include, or can optionally be combined with the subjectmatter of Example 1, to optionally include each negative differentialresistance device comprising a pair of back to back interband tunneldiodes serially connected by a junction configuration providing a lowresistance backward diode biased under Zener breakdown.

Example 3 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 1 or 2 to optionallyinclude at least one of the pair of devices comprising a pair ofinterband tunnel diodes.

Example 4 can include or use subject matter (such as an apparatus, amethod, a means for performing acts, or a device readable mediumincluding instructions that, when performed by the device, can cause thedevice to perform acts), such as can include or use an electronicdevice, comprising an integrated circuit including an integratedtransistor, an integrated capacitor coupled to the integratedtransistor, and a first tunnel diode, where the integrated transistor,the integrated capacitor, and the tunnel diode are arranged to provide amemory cell, the memory cell configured to store a bit value at least inpart using a capacitance provided by the tunnel diode.

Example 5 can include, or can optionally be combined with the subjectmatter of Example 4, to optionally include a dissipative load deviceelectrically coupled to a sensing node, where a terminal of theintegrated capacitor and a terminal of the first tunnel diode areelectrically coupled to the sensing node.

Example 6 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 4 or 5 to optionallyinclude a second integrated transistor electrically coupled to a sensingnode, where a terminal of the integrated capacitor and a terminal of thefirst tunnel diode are electrically coupled to the sensing node.

Example 7 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 4 through 6 to optionallyinclude a second tunnel diode electrically coupled to a sensing node,the second tunnel diode located between the sensing node and a firstpower supply node, where a first terminal of the integrated capacitorand a first terminal of the first tunnel diode are electrically coupledto the sensing node, and where a second terminal of the integratedcapacitor and a second terminal of the first tunnel diode areelectrically coupled to a second power supply node.

Example 8 can include or use subject matter (such as an apparatus, amethod, a means for performing acts, or a device readable mediumincluding instructions that, when performed by the device, can cause thedevice to perform acts), such as can include or use an electronicdevice, comprising an integrated circuit including an integratedtransistor, an integrated capacitor coupled to the integratedtransistor, and a tunnel diode pair, where the integrated transistor,the integrated capacitor, and the tunnel diode pair are arranged toprovide a memory cell, the memory cell configured to store a bit valueat least in part using a capacitance provided by a tunnel diode includedin the tunnel diode pair.

Example 9 can include, or can optionally be combined with the subjectmatter of Example 8, to optionally include an integrated capacitor andtunnel diode pair configured to establish a random access memory cellwhere the tunnel diode pair is configured to provide a self-restoringcurrent to retain a written bit value state without requiring a refresh.

Example 10 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 8 or 9 to optionallyinclude an integrated capacitor and at least one tunnel diode connectedin parallel.

Example 11 can include, or can optionally be combined with the subjectmatter of Example 10, to optionally include at least one tunnel diodeconnected in parallel with the integrated capacitor configured as adriver structure of the memory cell.

Example 12 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 8 through 11 to optionallyinclude at least one tunnel diode is arranged in a stacked configurationdirectly upon at least a portion of the transistor.

Example 13 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 8 through 12 to optionallyinclude at least one tunnel diode arranged in a stacked configurationlocated directly upon a source or drain region of the transistor.

Example 14 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 12 or 13 to optionallyinclude a transistor comprising a three-dimensional transistor, wherethe stacked configuration is located upon at least a portion of thethree-dimensional transistor.

Example 15 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 8 through 14 to optionallyinclude at least one tunnel diode arranged in a stacked configurationstacked configuration conformally wraps around at least a portion of athree dimensional transistor and is located in contact with a source ordrain region of the transistor.

Example 16 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 8 through 15 to optionallyinclude an integrated circuit comprises a silicon substrate.

Example 17 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 8 through 16 to optionallyinclude at least one tunnel diode comprising at least one interbandtunneling diode (ITD).

Example 18 can include, or can optionally be combined with the subjectmatter of Example 17, to optionally include an ITD comprising a resonantinterband tunnel diode comprising a heterojunction.

Example 19 can include, or can optionally be combined with the subjectmatter of Example 18, to optionally include and ITD comprising aresonant interband tunnel diode comprising a Si/SiGe heterojunction.

Example 20 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 17 through 19 to optionallyinclude a RITD including a delta-doping profile.

Example 21 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 17 through 20 to optionallyinclude an interband tunneling diode comprising a silicon-based RITDincluding a p-type delta doping of acceptors, an n-type delta doping ofdonors, a tunneling barrier located between the p-type and n-type deltadoping layers, where a portion of the tunneling barrier comprises analloy layer including at least two of silicon, germanium, carbon, andtin.

Example 22 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 17 through 20 to optionallyinclude an interband tunneling diode comprises a silicon-based RITDincluding a p-type delta doping of acceptors, an n-type delta doping ofdonors located on a first side of the p-type delta doping, a barriercomprising a first alloy layer including at least two of silicon,germanium, carbon, and tin located on a first side of the p-type deltadoping at least in part separating the p-type delta doping from then-type delta doping, and an interposed second alloy layer including atleast two of silicon, germanium, carbon, and tin adjacent the barrierfirst alloy layer and the p-type delta doping, the interposed secondalloy layer and the barrier first alloy layer defining a unitary layersubstantially containing the p-type delta doping.

Example 23 can include, or can optionally be combined with the subjectmatter of Example 22 to optionally include a first alloy layer includinga first mole fractions of constituents, and a second alloy layerincluding a different second mole fractions of constituents.

Example 24 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 20 through 23 to optionallyinclude an interband tunneling diode including a silicon-based RITDincluding carbon doping around a boron-doped delta-doping layer.

Example 25 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 8 through 24 to optionallyinclude back-to-back interband tunnel diodes connected via a lowresistance backward diode junction.

Example 26 can include, or can optionally be combined with the subjectmatter of Example 25 to optionally include a low resistance backwarddiode junction comprising a delta-doping profile.

Example 27 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 8 through 26 to optionallyinclude a capacitor comprising a trench capacitor.

Example 28 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 8 through 27 to optionallyinclude a capacitor comprising a stacked capacitor.

Example 29 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 8 through 28 to optionallyinclude at least one tunnel diode included in the tunnel diode pairincluding a symmetric tunnel diode structure comprising back-to-backinterband tunnel diodes to provide symmetric current-voltagecharacteristics around a zero bias point.

Example 30 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 8 through 29 to optionallyinclude two additional transistors arranged in a gain cell configurationto provide gain cell enhancement to the memory cell.

Example 31 can include subject matter (such as an apparatus, a method, ameans for performing acts, or a machine readable medium includinginstructions that, when performed by the machine, that can cause themachine to perform acts), such as can include a method of fabricating aninterband tunneling diode for use in any of the structures describedherein, the method comprising forming a first conductivity type layer ona substrate, forming a first confinement layer next to the firstconductivity type layer, forming a tunneling layer next to the firstconfinement layer, forming a second confinement layer next to thetunneling layer, and forming an opposite second conductivity type layernext to the second confinement layer.

Example 32 can include, or can optionally be combined with the subjectmatter of Example 31, to optionally include a first conductivity typethat is p-type, and where an opposite second conductivity type isn-type.

Example 33 can include, or can optionally be combined with the subjectmatter of Example 31, to optionally include a first conductivity typethat is n-type, and where an opposite second conductivity type isp-type.

Example 34 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 31 through 33 to optionallyinclude first and second confinement layers, and the tunneling layer aregrown epitaxially. Example 35 can include, or can optionally be combinedwith the subject matter of one or any combination of Examples 31 through34 to optionally include that the first confinement layer, the secondconfinement layer, and the tunneling layer are grown at a rate fromabout 0.001-10 nm/s.

Example 36 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 31 through 34 to optionallyinclude that the first confinement layer, the second confinement layer,and the tunneling layer are grown at a rate of 0.01-1 nm/s.

Example 37 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 31 through 34 to optionallyinclude that the first confinement layer, the second confinement layer,and the tunneling layer are grown at a rate of 0.05-0.2 nm/s.

Example 38 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 31 through 34 to optionallyinclude that the first and second confinement layers, and the tunnelinglayer are grown in a molecular beam epitaxial (MBE) growth system.

Example 39 can include, or can optionally be combined with the subjectmatter of Example 38, to optionally include that the molecular beamepitaxial (MBE) growth system is maintained at a pressure of 1×10⁻⁶ and1×10⁻¹¹ Pa during growth.

Example 40 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 38 or 39 to optionallyinclude that molecular beam epitaxial (MBE) growth system maintains asubstrate temperature between 50° C. and 900° C. during growth of theepitaxial layers.

Example 41 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 31 through 33 to optionallyinclude that the first and second confinement layers, and the tunnelinglayer are grown using chemical vapor deposition (CVD).

Example 42 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 31 through 41 to optionallyinclude heat treating the interband tunneling diode during or aftergrowth of the first and second confinement layers, and the tunnelinglayer.

Example 43 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 31 through 42 to optionallyinclude lowering a substrate temperature before or during growth of thefirst and second confinement layers, and the tunneling layer.

Example 44 can include subject matter (such as an apparatus, a method, ameans for performing acts, or a machine readable medium includinginstructions that, when performed by the machine, that can cause themachine to perform acts), such as can include a method of fabricating aninterband tunneling diode for use in any of the structures describedherein, the method comprising forming a first conductivity type layer ona substrate, forming a first confinement layer next to the firstconductivity type layer, forming a first low doped spacer layer next tothe first confinement layer, forming a tunneling layer next to the firstlow doped spacer layer, forming a second low doped spacer layer next tothe tunneling layer, forming a second confinement layer next to thesecond low doped spacer layer, and forming an opposite secondconductivity type layer next to the second confinement layer.

Example 45 can include, or can optionally be combined with the subjectmatter of Example 44, to optionally include a first conductivity typethat is p-type, and where an opposite second conductivity type isn-type.

Example 46 can include, or can optionally be combined with the subjectmatter of Example 44, to optionally include a first conductivity typethat is n-type, and where an opposite second conductivity type isp-type.

Example 47 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 44 through 46 to optionallyinclude heat treating the interband tunneling diode during or aftergrowth of the first and second confinement layers, the first and secondlow doped spacer layers, and the tunneling layer.

Example 48 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 44 through 47 to optionallyinclude that the first and second confinement layers, the first andsecond low doped spacer layers and the tunneling layer are grownepitaxially.

Example 49 can include, or can optionally be combined with the subjectmatter of Example 48, to optionally include that the first confinementand second confinement layers, the first and second low doped spacerlayers and the tunneling layer are grown at a rate of 0.001-10 nm/s.

Example 50 can include, or can optionally be combined with the subjectmatter of Example 48, to optionally include that the first confinementand second confinement layers, the first and second low doped spacerlayers and the tunneling layer are grown at a rate of 0.01-1 nm/s.

Example 51 can include, or can optionally be combined with the subjectmatter of Example 48, to optionally include that the first confinementand second confinement layers, the first and second low doped spacerlayers and the tunneling layer are grown at a rate of 0.05-0.2 nm/s.

Example 52 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 48 through 51 to optionallyinclude that the first and second confinement layers, the first andsecond low doped spacer layers, and the tunneling layer are grown in amolecular beam epitaxial (MBE) growth system.

Example 53 can include, or can optionally be combined with the subjectmatter of Example 51, to optionally include that the molecular beamepitaxial (MBE) growth system is maintained at a pressure of 1×10⁻⁶ and1×10¹¹ Pa during growth.

Example 54 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 52 or 53 to optionallyinclude that the molecular beam epitaxial (MBE) growth system maintainsa substrate temperature between 50° C. and 900° C. during growth of theepitaxial layers.

Example 55 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 44 through 47 to optionallyinclude that the first and second confinement layers, the first andsecond low doped spacer layers, and the tunneling layer are grown usingchemical vapor deposition (CVD).

Example 56 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 44 through 48 to optionallyinclude, during or after growth of the tunneling layers of the diode,annealing the diode using an inert or reducing gas ambient at atemperature in the range of 300° C. to 1000° C.

Example 57 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 44 through 48 to optionallyinclude, during or after growth of the tunneling layers of the diode,annealing the diode using an inert or reducing gas ambient at atemperature in the range of 500° C. to 900° C.

Example 58 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 44 through 48 to optionallyinclude heat treating the diode during or after the growth of thetunneling layers of the diode.

Example 59 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 44 through 48 to optionallyinclude annealing the diode using an inert or reducing gas ambient.

Example 60 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 44 through 48 to optionallyinclude annealing the diode at a temperature in the range of 300° C. to1000° C.

Example 61 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 44 through 48 to optionallyinclude annealing the diode at a temperature in the range of 450° C. to900° C.

Example 62 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 44 through 48 to optionallyinclude annealing the diode at a temperature in the range of 600° C. to800° C.

Example 63 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 44 through 48 to optionallyinclude annealing the diode for up to 6 hours.

Example 64 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 44 through 48 to optionallyinclude the diode for up to 1 hour.

Example 65 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 44 through 48 to optionallyinclude the diode for up to 10 minutes.

Example 66 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 44 through 48 to optionallyinclude annealing the diode for up to 2 minutes.

Example 67 can include subject matter (such as an apparatus, a method, ameans for performing acts, or a machine readable medium includinginstructions that, when performed by the machine, that can cause themachine to perform acts), such as can include a method of fabricating aninterband tunneling diode comprising growing a p-type injector and ann-type injector epitaxially at reduced substrate temperature.

Example 68 can include, or can optionally be combined with the subjectmatter of Example 67, to optionally include growing the p-type injectorand n-type injector while maintaining a substrate temperature between 0°C. and 900° C.

Example 69 can include, or can optionally be combined with the subjectmatter of Example 68, to optionally include growing the p-type injectorand n-type injector while maintaining a substrate temperature between20° C. and 450° C.

Example 70 can include or use subject matter (such as an apparatus, amethod, a means for performing acts, or a device readable mediumincluding instructions that, when performed by the device, can cause thedevice to perform acts), such as can include or use a symmetricinterband tunnel diode device, comprising a bottom injector layerseparated by an offset from a bottom contact, a middle injector layer, abottom spacer located between the bottom injector and middle injectorlayers configured to establish a first tunnel barrier, a top injectorlayer separated by an offset from a top contact, a top spacer locatedbetween the top injector and middle injector layers configured toestablish a second tunnel barrier, where the bottom injector, middleinjector, and top injector layers form the ends of one of a p-i1-n-i2-pstructure or an n-i1-p-i2-n structure, where an i1 region of thep-i1-n-i2-p structure or the n-i1-p-i2-n structure includes at least oneintrinsic semiconductor material located between the bottom and middleinjectors, and where an i2 region in the p-i1-n-i2-p structure or then-i1-p-i2-n structure includes at least one intrinsic semiconductormaterial provided between the middle and top injectors.

Example 71 can include, or can optionally be combined with the subjectmatter of Example 70, to optionally include a first quantum wellestablished in contact with the bottom injector layer and in contactwith, or separated by an offset from, the first tunnel barrier, a secondquantum well established in contact with the middle injector layer andis also in contact with, or separated by an offset from, the first andsecond tunnel barriers, and a third quantum well established in contactwith the top injector layer and is also in contact with, or separated byan offset from, the second tunnel barrier.

Example 72 can include, or can optionally be combined with the subjectmatter of Example 71, to optionally include that at least one of thefirst, second, and third quantum wells comprises establishing an energyband offset at, or near, a heterojunction.

Example 73 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 71 or 72 to optionallyinclude that the quantum wells each comprise a highly-doped layer.

Example 74 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 71 through 73 to optionallyinclude that the quantum wells each include a delta doped layer.

Example 75 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 71 through 74 to optionallyinclude that the quantum wells are each doped above a concentration of10¹² cm⁻².

Example 76 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 71 through 74 to optionallyinclude that the quantum wells are each doped above a concentration of10¹³ cm⁻².

Example 77 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 71 through 76 to optionallyinclude that the quantum wells are each less than or equal to 10 nmthick.

Example 78 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 71 through 76 to optionallyinclude that the quantum wells are each less than or equal to 2.5 nmthick.

Example 79 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 71 through 78 to optionallyinclude that the quantum wells are configured to establish resonanttunneling between a respective quantum well having a first polarity andan opposite polarity injector layer.

Example 80 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 71 through 79 to optionallyinclude that one or more of the bottom injector layer, the middleinjector layer, the top injector layer, the bottom spacer, or the topspacer include one or more of a semiconductor material or an insulator.

Example 81 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 71 through 80 to optionallyinclude that one or more the bottom injector layer, the middle injectorlayer, the top injector layer, the bottom spacer, or the top spacerinclude a material compatible with silicon.

Example 82 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 71 through 80 to optionallyinclude that one or more the bottom injector layer, the middle injectorlayer, the top injector layer, the bottom spacer, or the top spacerinclude a Group IV alloy.

Example 83 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 71 through 80 to optionallyinclude that one or more the bottom injector layer, the middle injectorlayer, the top injector layer, the bottom spacer, or the top spacerinclude a species selected from the list comprising Si, Ge, C, Sn,Si_(1-x)C_(x), Si_(1-x)Sn_(x), Si_(1-x-y)Ge_(x)C_(y),Si_(1-x-y-z)Ge_(x)C_(y)Sn_(z), Si_(1-x)O_(x), Si_(1-x)N_(x),Al_(1-x)O_(x), and combinations thereof.

Example 84 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 71 through 83 to optionallyinclude that at least one of the first spacer or the second spacercomprises a tunnel barrier material doped below a concentration of 10¹⁷cm⁻³.

Example 85 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 71 through 84 to optionallyinclude that the tunnel barrier material is less than or equal to 50 nmthick.

Example 86 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 71 through 85 to optionallyinclude that the tunnel barrier material is less than or equal to 10 nmthick.

Example 87 can include or use subject matter (such as an apparatus, amethod, a means for performing acts, or a device readable mediumincluding instructions that, when performed by the device, can cause thedevice to perform acts), such as can include a method of fabricating asymmetric interband tunneling diode device for use in any of thestructures described herein, the method comprising forming a firstconductivity type layer on a substrate, forming a first confinementlayer next to the first conductivity type layer, forming a firstlow-doped tunneling spacer layer next to the first confinement layer ona side opposite the first conductivity type layer, forming a firstlow-doped tunneling layer next to the first low doped tunneling spacerlayer on a side opposite the first confinement layer, forming a secondlow-doped tunneling spacer layer next to the first-low doped tunnelinglayer on a side opposite the first low-doped tunneling spacer layer,forming a second confinement layer next to the second low-dopedtunneling spacer layer on a side opposite the first low-doped tunnelinglayer, forming a third low-doped tunneling spacer layer next to thesecond confinement layer on a side opposite the second low-dopedtunneling spacer layer, forming a third low-doped tunneling layer nextto the third low-doped tunneling spacer layer on a side opposite thesecond confinement layer, forming a third confinement layer next to thethird low-doped tunneling layer, and forming a second conductivity typelayer next to the third confinement layer.

Example 88 can include, or can optionally be combined with the subjectmatter of Example 87, to optionally include that the confinement layersare each fabricated by establishing an energy band offset at, or near, aheterojunction.

Example 89 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 87 or 88 to optionally thatthe confinement layers are each fabricated by forming a highly dopedlayer.

Example 90 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 87 through 89 to optionallyinclude that the confinement layers are each fabricated to include adelta-doped layer.

Example 91 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 87 through 90 to optionallyinclude that the third low-doped tunneling spacer layer next to thesecond confinement layer is grown under low segregation conditions.

Example 92 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 87 through 91 to optionallyinclude that the second low-doped tunneling layer next to the thirdlow-doped tunneling spacer layer is grown under high segregationconditions.

Example 93 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 87 through 92 to optionallyinclude that the first low-doped tunneling spacer layer next to thefirst confinement layer is grown under low segregation conditions.

Example 94 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 87 through 93 to optionallyinclude that the first low-doped tunneling layer next to the firstlow-doped tunneling spacer layer is grown under high segregationconditions.

Example 95 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 87 through 94 to optionallyinclude that the second conductivity type layer next to the thirdconfinement layer is first grown under low segregation conditionsfollowed by high segregation conditions.

Example 96 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 87 through 95 to optionallyinclude that respective layers are grown by molecular beam epitaxy.

Example 97 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 88 through 96 to optionallyinclude that the devices are grown by chemical vapor deposition.

Example 98 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 91, 93, 95, or 96 tooptionally include that the low segregation conditions include reducedsubstrate temperature.

Example 99 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 91, 93, 95, 96, or 98 tooptionally include that the low segregation conditions include a reducedsubstrate temperature, the temperature reduced by more than 100 degreesCelsius as compared to a temperature used for processing other activedevice layers.

Example 100 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 91, 93, 95, 96, 98, or 99to optionally include that the low segregation conditions include areduced substrate temperature, the temperature reduced by more than 200degrees Celsius as compared to a temperature used for processing otheractive device layers.

Example 101 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 91, 93, 95, 96, or 98through 100 to optionally include that the low segregation conditionsinclude a reduced substrate temperature, the temperature reduced by morethan 300 degrees Celsius as compared to a temperature used forprocessing other active device layers.

Example 102 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 92, 94 through 96, or 98through 101 to optionally include that the high segregation conditionsinclude normal to elevated substrate temperatures as compared to atemperature used for processing other active device layers.

Example 103 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 92, 94 through 96, or 98through 102 to optionally include that the high segregation conditionsinclude elevated substrate temperature.

Example 104 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 91, 93, 95, or 97 tooptionally include that wherein the low segregation conditions includedelevated reactor pressure for chemical vapor deposition.

Example 105 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 91, 93, 95, 97, or 104 tooptionally include that the low segregation conditions include elevatedreactor pressure up to atmospheric pressure for chemical vapordeposition.

Example 106 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 91, 93, 95, 97, 104 or 105to optionally include that the low segregation conditions includeelevated reactor pressure up to atmospheric pressure using ahydrogen-containing gas.

Example 107 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 92, 94, 97, or 104 through106 to optionally include that the high segregation conditions includereduced reactor pressure as compared to a reactor pressure used forprocessing other active device layers.

Example 108 can include or use subject matter (such as an apparatus, amethod, a means for performing acts, or a device readable mediumincluding instructions that, when performed by the device, can cause thedevice to perform acts), such as can include or use serially connectedinterband tunnel diode (ITD) devices for purposes of establishing twosequential negative differential resistances “humps” in acurrent-voltage relationship under forward bias, the serially connectedITD devices comprising a bottom injector layer separated by an offsetfrom a bottom contact, a lower middle injector layer, a bottom spacerlocated between the bottom injector and lower middle injector layersconfigured to establish a first tunnel barrier, an upper middle injectorlayer, an upper spacer located between the upper middle injector layerand the top injector layer separated by an offset from a top contact, atop spacer located between the top injector and upper middle injectorlayers configured to establish a second tunnel barrier, where the bottominjector, lower middle injector, upper middle injector, and top injectorlayers form the ends of one of a p-i1-n-i2-p-i3-n structure or ann-i1-p-i2-n-i3-p structure, where an i1 region of the p-i1-n-i2-p-i3-nstructure or the n-i1-p-i2-n-i3-p structure includes at least oneintrinsic semiconductor material located between the bottom and lowermiddle injectors, and where an i2 region in the p-i1-n-i2-p structure orthe n-i1-p-i2-n-i3-p structure includes at least one intrinsicsemiconductor material provided between the lower middle injector andupper middle injector, and at least one intrinsic semiconductor materialprovided between the upper middle injector and top injectors.

Example 109 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 108 to optionally includethree, four, five, six, seven, or even more serially connected interbandtunnel diodes to create three, four, five, six, seven, or even moresequential negative differential resistance devices, respectively.

Example 110 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 108 and 109 where theserially connected interband tunnel diodes are used as the load in amulti-state memory circuit.

Example 111 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 108, 109 and 110 where themulti-state memory circuit includes multiple serially connectedinterband tunnel diodes connected in parallel with an externalcapacitor.

Example 112 can include, or can optionally be combined with the subjectmatter of Example 108, 109, 110, and 111, to optionally include an ITDcomprising a resonant interband tunnel diode comprising aheterojunction.

Example 113 can include, or can optionally be combined with the subjectmatter of Examples 108 through 112, to optionally include and ITDcomprising a resonant interband tunnel diode comprising a Si/SiGeheterojunction.

Example 114 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 108 through 113 tooptionally include a RITD including a delta-doping profile.

Example 115 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 108 through 114 tooptionally include an interband tunneling diode comprising asilicon-based RITD including a p-type delta doping of acceptors, ann-type delta doping of donors, a tunneling barrier located between thep-type and n-type delta doping layers, where a portion of the tunnelingbarrier comprises an alloy layer including at least two of silicon,germanium, carbon, and tin.

Example 116 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 108 through 115 tooptionally include an interband tunneling diode comprises asilicon-based RITD including a p-type delta doping of acceptors, ann-type delta doping of donors located on a first side of the p-typedelta doping, a barrier comprising a first alloy layer including atleast two of silicon, germanium, carbon, and tin located on a first sideof the p-type delta doping at least in part separating the p-type deltadoping from the n-type delta doping, and an interposed second alloylayer including at least two of silicon, germanium, carbon, and tinadjacent the barrier first alloy layer and the p-type delta doping, theinterposed second alloy layer and the barrier first alloy layer defininga unitary layer substantially containing the p-type delta doping.

Example 117 can include, or can optionally be combined with the subjectmatter of Examples 108 through 116 to optionally include a first alloylayer including a first mole fractions of constituents, and a secondalloy layer including a different second mole fractions of constituents.

Example 118 can include or use subject matter (such as an apparatus, amethod, a means for performing acts, or a device readable mediumincluding instructions that, when performed by the device, can cause thedevice to perform acts), such as can include or use serially connectedinterband tunnel diode devices for purposes of two sequential negativedifferential resistances “humps” under forward bias for use in any ofthe structures described herein, the method comprising forming a firstconductivity type layer on a substrate, forming a first confinementlayer next to the first conductivity type layer, forming a firstlow-doped tunneling spacer layer next to the first confinement layer ona side opposite the first conductivity type layer, forming a firstlow-doped tunneling layer next to the first low doped tunneling spacerlayer on a side opposite the first confinement layer, forming a secondlow-doped tunneling spacer layer next to the first-low doped tunnelinglayer on a side opposite the first low-doped tunneling spacer layer,forming a second confinement layer next to the second low-dopedtunneling spacer layer on a side opposite the first low-doped tunnelinglayer, forming a third low-doped tunneling spacer layer next to thesecond confinement layer on a side opposite the second low-dopedtunneling spacer layer, forming a third low-doped tunneling layer nextto the third low-doped tunneling spacer layer on a side opposite thesecond confinement layer, forming a third confinement layer next to athird low-doped tunneling layer, forming a third conductivity type layernext to the third confinement layer, forming a fourth low-dopedtunneling spacer layer next to the third confinement layer on a sideopposite the third low-doped tunneling spacer layer, forming a fourthlow-doped tunneling layer next to the fourth low-doped tunneling spacerlayer on a side opposite the third confinement layer.

Example 119 can include, or can optionally be combined with the subjectmatter of Example 118, to optionally include that the confinement layersare each fabricated by establishing an energy band offset at, or near, aheterojunction.

Example 120 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 118 or 119 to optionallyinclude that the confinement layers are each fabricated by forming ahighly doped layer.

Example 121 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 118 through 120 tooptionally include that the confinement layers are each fabricated toinclude a delta-doped layer.

Example 122 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 108 through 121 tooptionally include three, four, five, six, seven, or even more seriallyconnected interband tunnel diodes to create three, four, five, six,seven, or even more sequential negative differential resistance devices,respectively.

Example 123 can include, or can optionally be combined with the subjectmatter of one or any combination of Examples 108 through 122 where theserially connected interband tunnel diodes are used as the load inmulti-state memory circuit.

Various Notes

Each of the non-limiting examples described herein can stand on its own,or can be combined in various permutations or combinations with one ormore of the other examples. The above detailed description includesreferences to the accompanying drawings, which form a part of thedetailed description. The drawings show, by way of illustration,specific embodiments in which the invention can be practiced. Theseembodiments are also referred to herein as “examples.” Such examples caninclude elements in addition to those shown or described. However, thepresent inventors also contemplate examples in which only those elementsshown or described are provided. Moreover, the present inventors alsocontemplate examples using any combination or permutation of thoseelements shown or described (or one or more aspects thereof), eitherwith respect to a particular example (or one or more aspects thereof),or with respect to other examples (or one or more aspects thereof) shownor described herein. In the event of inconsistent usages between thisdocument and any documents so incorporated by reference, the usage inthis document controls.

In this document, the terms “a” or “an” are used, as is common in patentdocuments, to include one or more than one, independent of any otherinstances or usages of “at least one” or “one or more.” In thisdocument, the term “or” is used to refer to a nonexclusive or, such that“A or B” includes “A but not B,” “B but not A,” and “A and B,” unlessotherwise indicated. In this document, the terms “including” and “inwhich” are used as the plain-English equivalents of the respective terms“comprising” and “wherein.” Also, in the following claims, the terms“including” and “comprising” are open-ended, that is, a system, device,article, composition, formulation, or process that includes elements inaddition to those listed after such a term in a claim are still deemedto fall within the scope of that claim. Moreover, in the followingclaims, the terms “first,” “second,” and “third,” etc. are used merelyas labels, and are not intended to impose numerical requirements ontheir objects. In this document, use of the phrasemetal-oxide-semiconductor in the context of CMOS or MOS devices orprocessing does not literally require that a metal gate is used for CMOSor MOS structures, but instead refers to the fact that a conductive gatematerial (e.g., polysilicon or another conductor) can be used. Forexample, conductors can include a metal, a silicide, or a semiconductormaterial (e.g., having doping to achieve a desired conductivity).

Method examples described herein can be machine or computer-implementedat least in part. Some examples can include a computer-readable mediumor machine-readable medium encoded with instructions operable toconfigure an electronic device to perform methods as described in theabove examples. An implementation of such methods can include code, suchas microcode, assembly language code, a higher-level language code, orthe like. Such code can include computer readable instructions forperforming various methods. The code may form portions of computerprogram products. Further, in an example, the code can be tangiblystored on one or more volatile, non-transitory, or non-volatile tangiblecomputer-readable media, such as during execution or at other times.Examples of these tangible computer-readable media can include, but arenot limited to, hard disks, removable magnetic disks, removable opticaldisks (e.g., compact disks and digital video disks), magnetic cassettes,memory cards or sticks, random access memories (RAMs), read onlymemories (ROMs), and the like.

The above description is intended to be illustrative, and notrestrictive. For example, the above-described examples (or one or moreaspects thereof) may be used in combination with each other. Otherembodiments can be used, such as by one of ordinary skill in the artupon reviewing the above description. The Abstract is provided to complywith 37 C.F.R. §1.72(b), to allow the reader to quickly ascertain thenature of the technical disclosure. It is submitted with theunderstanding that it will not be used to interpret or limit the scopeor meaning of the claims. Also, in the above Detailed Description,various features may be grouped together to streamline the disclosure.This should not be interpreted as intending that an unclaimed disclosedfeature is essential to any claim. Rather, inventive subject matter maylie in less than all features of a particular disclosed embodiment.Thus, the following claims are hereby incorporated into the DetailedDescription as examples or embodiments, with each claim standing on itsown as a separate embodiment, and it is contemplated that suchembodiments can be combined with each other in various combinations orpermutations. The scope of the invention should be determined withreference to the appended claims, along with the full scope ofequivalents to which such claims are entitled.

1. (canceled)
 2. A method, comprising forming an integrated circuitincluding: forming an integrated transistor; forming an integratedcapacitor coupled to the integrated transistor; and forming multiplenegative differential resistance (NDR) devices; wherein the integratedtransistor, the integrated capacitor, and the NDR devices are arrangedto provide a multi-state memory cell.
 3. The method of claim 2, whereinthe NDR devices comprise tunnel diodes.
 4. The method of claim 3,comprising coupling the integrated capacitor and at least one tunneldiode in parallel.
 5. The method of claim 3, comprising forming thetunnel diodes in a stacked configuration directly upon at least aportion of the transistor.
 6. The method of claim 3, wherein at leastone tunnel diode includes at least one resonant interband tunnelingdiode (RITD).